ESD : physics and devices
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Semiconductor device and process development, quality, reliability and failure analysis engineers will also find it an essential tool. In addition, both senior undergraduate and graduate students in microelectronics and IC design will find its numerous examples useful. ESD : Circuits and Devices. Steven H. The scaling of semiconductor devices from sub-micron to nanometer dimensions is driving the need for understanding the design of electrostatic discharge ESD circuits, and the response of these integrated circuits IC to ESD phenomena.
If the parasitic capacitance increases, the signal loss dramatically increases at high frequency, as shown in Figure 2 b. To mitigate the performance degradation caused by the parasitic capacitance, the ESD protection circuit must carefully design. For example, a typical specification for the parasitic capacitance of input terminal of a gigahertz IC is fF [ 15 ]. The unidirectional ESD protection device was a diode.
Esd, Physics and Devices by Steven H. Voldman | | Booktopia
The multi-finger structure can be realized by combining such single-finger structures with sharing drain and source regions between every two adjacent fingers. All the parasitic capacitance Coverlap , Cj , and Cjsw are given by the process. Besides the drain width, the Ln strongly affects the total capacitance. For high-frequency applications, the Ln needs to be optimized by reducing the contact rows, the enclosure of contacts, and the extension of silicide [ 22 , 23 ]. Therefore, a trade-off between the ESD robustness and the parasitic capacitance has to be found.
However, the parasitic capacitance of MOS-based ESD protection device is usually too large to be tolerable for the high-frequency circuits. The SCR device has been reported to be useful for ESD protection in high-frequency circuits due to its higher ESD robustness within a smaller layout area and lower parasitic capacitance [ 22 ]. The device structure of the SCR device is illustrated in Figure 6 b. This SCR triggers on at The main drawback of SCR device is the higher trigger voltage and thus the slower turn-on speed.
Research works have demonstrated that separation of the N-well and P-well junction can play an important role. Another alternative method to reduce the trigger voltage of an SCR device uses the substrate-triggered technique.
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Some circuit design techniques are reported to enhance the turn-on efficiency of SCR devices, such as the gate-coupled, substrate-triggered, diode-triggered, and gate-grounded-NMOS-triggered GGNMOS-triggered techniques [ 28 , 29 , 30 ]. Under normal circuit operating condition, the inductor can resonate with the parasitic capacitance, and hence the signal loss can be compensated. Once the dimension of SCR has been chosen, the inductance L can be designed to minimize the high-frequency performance degradation by using the following equation:.
Therefore, the required L for 30GHz applications is pH. The trigger voltage can be adjusted by adding or reducing the diode numbers.
Diode is a typical ESD protection device with unidirectional discharging path [ 32 , 33 ]. Besides the STI-bounded diodes, the gate-bounded diodes have been reported, as shown in Figure 11 d and e. In order to reduce the parasitic capacitance or provide the large signal-swing tolerance, the ESD protection diodes in stacked configuration have been presented [ 36 , 37 ], as shown in Figure 12 a.
The device cross-sectional views of the conventional stacked diodes are shown in Figure 12 b and c. With the stacked diodes, the junction capacitances are connected in series, and the overall parasitic capacitance becomes smaller. However, the stacked configuration is adverse to ESD protection because the overall turn-on resistance and the clamping voltage of the stacked diodes during ESD stresses are increased as well.
ESD protection circuit with stacked diodes. The stacked diodes with embedded SCR are illustrated in Figure In the beginning of ESD stress, the initial current will be discharged through the stacked diodes, and then the primary current will be discharged through the embedded SCR. We can find that turn-on resistance or the clamping voltage of single diode is much lower than that of the stacked diodes.
The embedded SCR can help to slightly reduce the turn-on resistance and the clamping voltage of the stacked diodes.
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In fact, some layout skills can be used to further improve the turn-on efficient of the stacked diodes with embedded SCR [ 40 ]. Recently, a similar structure of the stacked diodes with embedded SCR, where a resistor uses to separate two diodes, has been reported [ 41 ].
The resistor can also reduce the parasitic capacitance of the ESD protection circuit. Considering the simplified SCR model by using junction capacitances, as shown in Figure 15 c , the equivalent capacitance seen at anode or cathode of RTSCR can be calculated by the following equation:. To simplify the above equation, the junction capacitance is rewritten to CJ , and then the parasitic capacitance of the RTSCR can be expressed by the following equation:.
The SCR device in this ESD protection circuit still has the drawbacks of higher trigger voltage and the slower turn-on speed. The circuit design techniques, including the gate-coupled, substrate-triggered, diode-triggered, and GGNMOS-triggered techniques can be used to enhance the turn-on efficiency of SCR device. Recently, an SCR device with inductive triggering device has been presented [ 43 ].
In this design, the inductor provides a current path to trigger the SCR device, and it can also compensate the parasitic capacitance of ESD protection devices.